制造商: Xilinx
產(chǎn)品種類: FPGA - 現(xiàn)場可編程門陣列
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RoHS: 詳細(xì)信息
系列: XC6VLX550T
邏輯元件數(shù)量: 549888 LE
自適應(yīng)邏輯模塊 - ALM: 85920 ALM
嵌入式內(nèi)存: 22.22 Mbit
輸入/輸出端數(shù)量: 840 I/O
電源電壓-最小: 1 V
電源電壓-最大: 1 V
最小工作溫度: - 40 C
最大工作溫度: + 100 C
數(shù)據(jù)速率: 6.6 Gb/s
收發(fā)器數(shù)量: 36 Transceiver
安裝風(fēng)格: SMD/SMT
封裝 / 箱體: FCBGA-1759
商標(biāo): Xilinx
分布式RAM: 6200 kbit
內(nèi)嵌式塊RAM - EBR: 22752 kbit
最大工作頻率: 1.6 GHz
濕度敏感性: Yes
邏輯數(shù)組塊數(shù)量——LAB: 42960 LAB
工作電源電壓: 1 V
產(chǎn)品類型: FPGA - Field Programmable Gate Array
12
子類別: Programmable Logic ICs
商標(biāo)名: Virtex
? Virtex-6 LXT FPGAs: High-performance logic with advanced serial connectivity ? Virtex-6 SXT FPGAs: Highest signal processing capability with advanced serial connectivity ? Virtex-6 HXT FPGAs: Highest bandwidth serial connectivity ? Compatibility across sub-families ? LXT and SXT devices are footprint compatible in the same package ? Advanced, high-performance FPGA Logic ? Real 6-input look-up table (LUT) technology ? Dual LUT5 (5-input LUT) option ? LUT/dual flip-flop pair for applications requiring rich register mix ? Improved routing efficiency ? 64-bit (or two 32-bit) distributed LUT RAM option per 6-input LUT ? SRL32/dual SRL16 with registered outputs option ? Powerful mixed-mode clock managers (MMCM) ? MMCM blocks provide zero-delay buffering, frequency synthesis, clock-phase shifting, inputjitter filtering, and phase-matched clock division ? 36-Kb block RAM/FIFOs ? Dual-port RAM blocks ? Programmable - Dual-port widths up to 36 bits - Simple dual-port widths up to 72 bits ? Enhanced programmable FIFO logic ? Built-in optional error-correction circuitry ? Optionally use each block as two independent 18 Kb blocks ? High-performance parallel SelectIO? technology ? 1.2 to 2.5V I/O operation ? Source-synchronous interfacing using ChipSync? technology ? Digitally controlled impedance (DCI) active termination ? Flexible fine-grained I/O banking ? High-speed memory interface support with integrated write-leveling capability